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多时钟域设计的一个难题是如何避免亚稳态的产生。An important problem in multi-clock domain design is how to avoid metastability.

避免亚稳态问题及空满控制信号的产生是异步FIFO设计的两个关键。Metastability and how to generate empty and full flag correctly is key in the design of asynchronous FIFO.

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这种退火脆性是由非晶态合金亚稳特性决定的结构弛豫所致。This annealing embrittlement is caused by structural relaxation which is controlled by the metastability of amorphous alloys.

提供的设计技巧和优化手段在实践中可以很好地抑制亚稳态，提高系统可靠性。Using the proposed design techniques and optimization methods, metastability could be controlled and system reliability could be improved.

两个异步单元之间的联接、或是一个信号引入一与之异步的系统时，可能会引起亚稳态而导致故障。Metastability failure may occur when a connection is needed between two asynchronous units, or a digital signal is sampled by another asynchronous system.

只要选择适当的高频时钟频率和电路参数，亚稳态可以得到完全消除。In Conclusion, so long as select appropriately time of delay and High-frequency clock, the occurrence of metastability in circuit could be totally avoided.

绝大部分ASIC设计工程师在实际工作中都会遇到多时钟域设计的问题，多时钟域设计的一个难题是如何避免亚稳态的产生。Most of the ASIC" s ever designed are driven by multiple asynchronous clocks. An important problem in multi-clock do-main design is how to avoid metastability."

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指出了设计中的“竞争冒险”和饱受困扰之苦的“亚稳态”问题，分析了产生机理，并给出了常用的解决措施。Finally, this paper has pointed out "race and hazard" as well as "metastability" problem, analyzed producing mechanism, and given some general solution measures.

固体炸药是一种蕴含高能量的亚稳态物质，遇外界刺激达到一定阈值就会发生强烈化学反应。But solid explosives are high-energy metastability materials, when encountered external stimulation to the reactive threshold, a strong chemical reaction will occur.

探讨了亚稳态的产生机制，对FPGA设计中的亚稳态进行分析，针对FPGA设计中的亚稳态问题，给出了一系列行之有效的解决方法。Generation mechanism of metastability was discussed, and metastability in FPGA design was analyzed. A number of effective solutions were presented to solve the problem of metastability.

针对通信过程中多时钟域之间的亚稳态现象，分析了几种同步器在集成电路异步设计中的应用。During the process of communication between different clock domains, metastability is likely to happen. This paper discusses several applications of different synchronizers in IC asynchronous design.