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我在设计中采用软件的方式来消除抖动。I use the software in the design approach to the elimination of jitter.

静态抖动缓冲器是基于硬件的，它是由厂家来配置的。A static jitter buffer is hardware-based and is configured by the manufactures.

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这点，从另一个角度来说，缩减了眼图的扩展度，并增加总量颤动。This, in turn, reduces the data eye opening and increases the amount of jitter.

廖每个独立的接收和传输信道和一个内置的抖动衰减器。Each LIU has independent receive and transmit paths and a built-in jitter attenuator.

并对光杆横向加速度进行了直接检测，得到光杆抖动信息。It detects the lateral acceleration of the polished rod to get the jitter information.

为了保证键动作一次，仅进行一次处理，必须采取措施以消除抖动。In order to ensure a key action, only a treatment, must take measures to eliminate jitter.

通过锁相环路的应用可减小延时后的脉冲抖动并得到准确的延时时间。The delayed pulse jitter is reduced and the exact delay time is obtained by using the PLL.

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本文实现了在20千米实际双向光纤通路下减小时延抖动的补偿系统。A novel timing jitter reduction system over a round trip 20-km urban fiber link is reported.

本文研制了一个基于加速度传感器的光杆抖动检测系统。This paper has developed a polished rod jitter detection system based on acceleration sensor.

三角测量技术，为确定长码型PRBS31抖动构成提供了快速高效的方法。Fast, effective method for determining long pattern PRBS31 jitter composition with triangulation.

为了尽量减少抖动的锁相环，建议，以避免在测试输出的积极信号。In order to minimize the PLL jitter , it is recommended to avoid active signal on the TEST output.

研究了三电极球隙的延迟和抖动特性。The delay and jitter characteristics of the three electrode spark gap weres studied in this paper.

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这一干扰抖动的存在，会使近年来提出的减小抖动方法的抖动转移特性劣化。This interference jitter can degrade the performance of the newly introduced reduce-jitter method.

并且新的调度系统模型无时间死线、抖动大小限制，适用范围更广。Further, it is wide in application for the scheduling model without the limit of deadline and jitter.

选配抖动地图，提供了快速抖动分解及DUT输入准确压力校准功能。Optional Jitter Map provides fast jitter decomposition, accurate stress calibration at the DUT input.

此方法有效地解决了泄漏的量化抖动问题以及复杂的泄漏控制问题。It greatly reduces the quantization jitter in pointer leaking and also the complexity of leaking control.

磁挥笔赢得大多数读者除了停止和去抖动或刷卡吨，将会给一个完整的错误读数。Most magnetic swipes readers wont except JITTER or STOPS and go SWIPES, will give a complete error reading.

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像素时钟输出频率范围从10MHz到140MHz的采样250ps的峰峰值抖动。Pixel clock output frequencies range from 10MHz to 140MHz with sampling clock jitter of 250ps peak to peak.

实验证明，此算法能够在保留点目标低频运动的同时有效地滤除高频抖动。The filter can remove high-frequency jitter effectively and keeping low-frequency movement at the same time.

而此篇论文使用了双迴路追溯路径来达到更好的抖动效能。This Thesis presents a CDR architecture which has dual loop tracking path to achieve better jitter performance.