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利用MFC编写一个简单的四则运算器。Using MFC to write a simple arithmetic device.

比较这一逻辑运算是运算器主要的运算活动之一。Comparison is one of the main activities of the ALU.

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计算机组成原理的一个浮点数运算器。Computer principle of a floating point arithmetic unit.

所以这是个极端复杂的运算器So, it's an extraordinarily complicated computing device.

在运算器中的寄存器一般为立即存取寄存器。The register inside APU is generally a zero access register.

如此，我们遮蔽这个运算器指标以表明这是资料。Thus we have shaded the operand specifier to show that it is data.

现在让我们来看看在顶点着色运算器中这些寄存器和指令如何被典型的运用。Now let's see how these registers and instructions are typically used in the vertex shader ALU.

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介绍了基于FPGA技术的浮点运算器的设计与实现。Designing a floating point calculator using FPGA technology may shorten the development cycle of product.

这种检错方法不但能检测运算结果故障，还能够检测运算器故障、时序故障及时间故障。The method can detect not only operation errors, but also operand errors, sequence errors and time errors.

并将模加、模乘、模平方运算集中设计成了一个多功能运算器，使控制电路更加简单。The modular addition, modular multiple and modular square are placed in the ALU to simplify the controller.

这个IP模型主要由运算器模块，控制器模块，时钟模块和端口模块四个部分组成。The IP core is made up of four modules, which are alu_module, control_ module, timer_module and port_module.

提出了一种面积优先的多功能、可重组的大数值运算器设计方法。An area-first design method for multifunctional and reconfigurable large number calculators was brought forward.

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取控造器比拟，运算器接收节制器的命令进举动息。Compared with the control unit, the arithmetic logic unit accepts the command of the control unit to carry through action.

在设计数字信号处理器时我们经常要设计高性能的乘累加运算器。Usually we have to design the high performance multiply accumulation cell when we are designing a digital signal processor.

多用书写板是由基板、书写板和运算器组成，运算器固定在基板上。The multipurpose writing plate is composed of a baseplate, a writing board and an arithmetic unit. The arithmetic unit is fixed to the baseplate.

缓冲存储器周期的一部分，在这期间，逻辑与算术运算器必须中止操作或不能与存储器传输信息。A portion of the buffer cycle in which the logic or arithmetic unit must cease operation or neither will be able to communicate with the memory unit.

也就是说，运算器入言的全体操作是有把持器领没的掌握信号去指挥的，所以它是履行部件。That is to say, all the operations of what the arithmetic unit goes along are commanded by the control signal the unit sends off, so it is an executing component.

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通过时域和频域的数字信号处理的方法，用FPGA器件构成卷积器或FFT运算器，还原出与雷达信号形式相关的杂波信号。And it is resumed to clutter signal specified to the environment using time domain and spectrum domain algorithm which is FFT calculator or convolator based on FPGA device.

为了减少运算器件，节约FPGA的资源，将模逆运算转化为模乘运算和模平方运算的迭代。In order to reduce the number of the apparatus and the size of the FPGA, the modular inversion is replaced with the iteration of the modular multiple and the modular square.

文中详细介绍通用运算器模块的设计及实现，分析了设计中的关键技术和解决的途径。The paper presents in detail the design and the realization of the universal operation module, and analyzes the key techniques in design and the way for solving the problems.